A Novel 3D-SRAM Architecture Based on Vertical GAA Transistors for Advanced AI and Edge Computing Applications

We present a novel 3D-SRAM architecture based on vertical gate-all-around (VGAA) transistors to address the limitations of conventional planar static random access memory (SRAM) in advanced technology nodes. The proposed bit cell leverages four vertically aligned silicon pillars to implement six transistors, achieving approximately 70% area reduction compared to conventional 3-nm-node SRAM. TCAD simulations were conducted to optimize device parameters, revealing that channel length (L<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CH</sub>) and spacer length (L<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SP</sub>) significantly affect noise margins and standby power consumption. Statistical analysis incorporating work function variation (WFV) demonstrated that write operations are particularly vulnerable to variability, necessitating further optimization. By exploiting the structural flexibility of VGAA design, we fine-tuned the cell ratio (CR) and pull-up ratio (PR) to meet the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6\sigma $</tex-math> </inline-formula> yield criterion for both read and write operations at V<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{\text {DD}} = {0.6}$</tex-math> </inline-formula> V. The resulting configuration not only improves V<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</sub> and write stability but also maintains low standby power consumption. These findings highlight the proposed VGAA-based 3D-SRAM as a promising candidate for energy-efficient and compact memory solutions in artificial intelligence (AI) and edge computing systems.