Structure optimization and calibration of a frequency synthesizer with a low-level phase noise in the phase-locked loop (pll)

The problem of designing a PLL frequency synthesizer with a low level of phase noise is considered. The main technical limits of traditional frequency synthesizer implementations, as well as an analysis and comparison of the known engineering solutions for the structures of designing frequency synthesizers are provided. The structure of a low-noise synthesizer with PLL frequency translation is considered. Two main methods for calibrating a frequency synthesizer in IC with an integrated voltage-controlled oscillator are presented. Useful practical recommendations and an illustrative example are provided.