DESIGN A LIFTING SCHEME BASED AREA AND DELAY OPTIMIZED VLSI ARCHITECTURE FOR DWT

Wavelet analysis is based on the principle of scale analysis. Actually, according to some wavelet specialists, employing wavelets is akin to taking a certain stance when it comes to data processing. For the purpose of representing data or other functions, wavelets are functions that meet specific mathematical conditions. Utilizing a carry select adder, a separable pipeline architecture is described in this study for the quick computation of the 2D DWT with little space and latency. Appropriate 2-D DWT filtering process design and effective data transfer between 2 D DWT filters yield reduced latency and little area.

Publication Details

Journal
Zenodo (CERN European Organization for Nuclear Research)
Published
2025-10-09
DOI
https://doi.org/10.5281/zenodo.17300977
Primary Topic
Yersinia bacterium, plague, ectoparasites research
Type
article
Field-Weighted Citation Impact
0.00
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article

DESIGN A LIFTING SCHEME BASED AREA AND DELAY OPTIMIZED VLSI ARCHITECTURE FOR DWT

Zenodo (CERN European Organization for Nuclear Research)
Yersinia bacterium, plague, ectoparasites research
article

DESIGN A LIFTING SCHEME BASED AREA AND DELAY OPTIMIZED VLSI ARCHITECTURE FOR DWT

article en

Abstract

Wavelet analysis is based on the principle of scale analysis. Actually, according to some wavelet specialists, employing wavelets is akin to taking a certain stance when it comes to data processing. For the purpose of representing data or other functions, wavelets are functions that meet specific mathematical conditions. Utilizing a carry select adder, a separable pipeline architecture is described in this study for the quick computation of the 2D DWT with little space and latency. Appropriate 2-D DWT filtering process design and effective data transfer between 2 D DWT filters yield reduced latency and little area.

Zenodo (CERN European Organization for Nuclear Research)
Industry, innovation and infrastructure
Openalex Percentile: Top 34%
Yersinia bacterium, plague, ectoparasites research
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DESIGN A LIFTING SCHEME BASED AREA AND DELAY OPTIMIZED VLSI ARCHITECTURE FOR DWT · Zenodo (CERN European Organization for Nuclear Research) (2025) | TGRS Research Map | TGRS