Surface Roughness and Dislocation Defects Improvement in Monolithic High-Mobility Ge CFETs Through Vacuum Annealing

In this work, we experimentally demonstrate a high-mobility Ge Complementary FET (CFET) fabricated by a wafer bonding technique. CMOS-friendly manufacturing processes, including vacuum annealing and TMAH-based etching solutions, have been developed to acquire high-quality suspended Ge channels. Significant improvement of surface roughness by at least 64% and elimination of mismatch dislocation of Ge nanosheets generated during Ge/Si epitaxial growth has been achieved. The suspended Ge channels exhibit nearly defect-free quality, leading to high-performance vertically stacked 3-layer pFET/3-layer nFET nanosheet (P-3NS/N-3NS) Ge CFET. Well-behaved Ge nanosheet p/nFETs performance and excellent voltage transfer characteristics (VTC) behaviors of Ge CFET inverters have been successfully demonstrated.