Device-Circuit Cooperative Design and Assessment of Scaled Bulk-Si DTMOS for Embedded Low-Operating-Power Applications

Low-power (LP) device design is a dominant direction in modern electronics, as reflected in recent semiconductor technology roadmaps. The dynamic-threshold metal-oxide-semiconductor field-effect transistor (DTMOS), which dynamically modulates threshold voltage by tying the gate and the body, offers inherently low drive voltage. While DTMOS has been widely studied on silicon-on-insulator (SOI) platforms, its extension to scaled bulk-Si technology remains largely unexplored. In this work, we provide the first comprehensive investigation of bulk-Si DTMOS physics and operation. Using calibrated technology computer-aided design (TCAD) and circuit simulations, we show that bulk-Si DTMOS not only suppresses short-channel effects (SCEs) more effectively than conventional bulk MOSFETs, but also delivers improved subthreshold swing and enhanced on/off ratios as scaling intensifies where conventional devices suffer from severe leakage. Furthermore, we introduce a body-biasing scheme with a limiting transistor that decouples gate and body at high <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub>, enabling strong on-state performances without reliability degradation. These results establish bulk-Si DTMOS as a scalable and cost-effective candidate bridging low-power and high-performance (HP) CMOS applications.