An RSFQ Physical Synthesis Framework for Superconductor 3-D Logic Process

Rapid Single Flux Quantum (RSFQ) logic is a digital logic based on superconductor fabrication technology, offering significant potential in high-performance computing, particularly in the design of central processing units for superconducting neuromorphic and quantum computing. The elementary components of RSFQ circuits, the Josephson junction (JJ), provides high-speed and low-power switching properties, allowing RSFQ digital systems to operate at tens of GHz with power consumption at the milliwatt level. Moreover, the simplicity of the JJ's physical structure facilitates the possibility of 3D stacked logic designs using superconductor technology. However, the pulse-based Boolean gates in RSFQ logic introduce unique challenges in layout design, clock tree structure, and the physical and timing characteristics of wiring components compared to CMOS logic. These differences lead to complexities in physical design automation, which are not compatible with existing automation frameworks and tools. This paper presents a physical synthesis of RSFQ logic, offering integrated methods for partition, placement, clock tree synthesis, and hybrid routing, all designed for the RSFQ cell library and supporting physical synthesis for 3D stacked logic process. The integrated physical synthesis algorithms are capable of minimizing the area overhead of RSFQ circuits while maximizing their clock frequency and power efficiency. The proposed framework has demonstrated promising optimization results on several benchmark circuits, achieving post-routing clock frequencies up to 72.5 GHz and power consumption levels ranging from microwatts to milliwatts.