BEOL-Compatible Co-Sputtered $\text{Te}_{\text{1}-x}\text{Se}_{x}$ p-FETs With Bandgap Engineering Enabling Monolithic 3-D CMOS Logic and Memory

We report back-end-of-line (BEOL) compatible p-type <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{tellurium}_{1-x}\text{selenium}_{x}$</tex-math> </inline-formula> (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{Te}_{1-\textit{x}}\text{Se}_{\textit{x}}$</tex-math> </inline-formula>) field-effect transistors (FETs) with aggressively scaled channel length down to 50 nm, fabricated via a novel Te–Se co-sputtering method. Se incorporation effectively widens the bandgap, as confirmed by density functional theory (DFT) calculations, resulting in suppressed <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small>-state current and enhanced device performance. Comprehensive experimental characterizations—including contact barrier height extraction, temperature-dependent transport measurements from 295 K down to 77 K, and bias temperature instability (BTI) analysis—demonstrate that Te<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{{0}.{8}}$</tex-math> </inline-formula>Se<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{{0}.{2}}$</tex-math> </inline-formula> FETs achieve a mobility of 24 cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>/V<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\cdot $</tex-math> </inline-formula>s, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {on}}$</tex-math> </inline-formula>/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {off}}$</tex-math> </inline-formula> ratio exceeding <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{{4}}$</tex-math> </inline-formula>, and subthreshold swing (SS) near 300 mV/Dec. By integrating with indium–gallium–zinc-oxide (IGZO) n-FETs through monolithic 3-D stacking, we realize vertically stacked circuits: an n–p dynamic random-access-memory (DRAM) cell with retention exceeding 1000 s, a short-channel complementary FET (CFET) inverter showing a voltage gain of 38 at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {DD}} = 2.5$</tex-math> </inline-formula> V, and a compact CFET-structured static random-access-memory (SRAM) cell with a 33% area reduction compared to conventional 6 T SRAM. This work demonstrates co-sputtered <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{Te}_{1-\textit{x}}\text{Se}_{x}$</tex-math> </inline-formula> as a promising p-type channel for high-density, energy-efficient monolithic 3-D (M3D) integration.