Contacted-Poly-Pitch (CPP) Scaling Limitations of Si Gate-All-Around Nanosheet (GAA-NS) Devices

Contacted-poly-pitch (CPP) scalability of gate-all-around (GAA) nanosheet (NS) device is investigated in detail. Combination of NS thickness (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${T}_{\text {NS}}$</tex-math> </inline-formula>) and junction abruptness (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\delta $</tex-math> </inline-formula>) allow for spacer thickness (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${T}_{\text {SP}}$</tex-math> </inline-formula>) and gate-length (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}_{G}$</tex-math> </inline-formula>) scaling. Contact-length <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}_{\text {CNT}}$</tex-math> </inline-formula> scaling does not affect intrinsic performance, but scaling is limited by middle-of-line and interface resistivity. Using an extensively calibrated advanced transport model combined with the transistor design-technology co-optimization (DTCO) flow we account for accurate device and circuit intrinsics and parasitics. We highlight the trade-off between <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${T}_{\text {SP}}$</tex-math> </inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}_{G}$</tex-math> </inline-formula> scaling whereby <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}_{G}$</tex-math> </inline-formula> can be scaled more aggressively if <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${T}_{\text {SP}}$</tex-math> </inline-formula> can be relaxed. <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${T}_{\text {NS}}$</tex-math> </inline-formula> can be scaled to ~3.5 nm maintaining iso-performance allowing for a minimum CPP of ~38 nm at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}_{G}~\sim 10$</tex-math> </inline-formula> nm. Aggressively improving <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\delta -$</tex-math> </inline-formula> can further allow CPP scaling to ~34 nm (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}_{G}~\sim 6$</tex-math> </inline-formula> nm), though <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${T}_{\text {NS}}$</tex-math> </inline-formula> scaling gain saturates due to severe transport degradation.

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Publication Details

Journal
IEEE Transactions on Electron Devices
Published
2025-10-07
DOI
https://doi.org/10.1109/ted.2025.3615917
Citations
1
Primary Topic
Aviation Industry Analysis and Trends
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article
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article

Contacted-Poly-Pitch (CPP) Scaling Limitations of Si Gate-All-Around Nanosheet (GAA-NS) Devices

1 citations
IEEE Transactions on Electron Devices
Aviation Industry Analysis and Trends
3.09
article

Contacted-Poly-Pitch (CPP) Scaling Limitations of Si Gate-All-Around Nanosheet (GAA-NS) Devices

article en
1 citations

Abstract

Contacted-poly-pitch (CPP) scalability of gate-all-around (GAA) nanosheet (NS) device is investigated in detail. Combination of NS thickness (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${T}_{\text {NS}}$</tex-math> </inline-formula>) and junction abruptness (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\delta $</tex-math> </inline-formula>) allow for spacer thickness (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${T}_{\text {SP}}$</tex-math> </inline-formula>) and gate-length (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}_{G}$</tex-math> </inline-formula>) scaling. Contact-length <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}_{\text {CNT}}$</tex-math> </inline-formula> scaling does not affect intrinsic performance, but scaling is limited by middle-of-line and interface resistivity. Using an extensively calibrated advanced transport model combined with the transistor design-technology co-optimization (DTCO) flow we account for accurate device and circuit intrinsics and parasitics. We highlight the trade-off between <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${T}_{\text {SP}}$</tex-math> </inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}_{G}$</tex-math> </inline-formula> scaling whereby <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}_{G}$</tex-math> </inline-formula> can be scaled more aggressively if <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${T}_{\text {SP}}$</tex-math> </inline-formula> can be relaxed. <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${T}_{\text {NS}}$</tex-math> </inline-formula> can be scaled to ~3.5 nm maintaining iso-performance allowing for a minimum CPP of ~38 nm at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}_{G}~\sim 10$</tex-math> </inline-formula> nm. Aggressively improving <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\delta -$</tex-math> </inline-formula> can further allow CPP scaling to ~34 nm (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}_{G}~\sim 6$</tex-math> </inline-formula> nm), though <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${T}_{\text {NS}}$</tex-math> </inline-formula> scaling gain saturates due to severe transport degradation.

IEEE Transactions on Electron DevicesVol. 72(12)
Deutsche Telekom (Austria) (AT), Huawei Technologies (United States) (US)
Affordable and clean energy
Openalex Percentile: Top 6%
Aviation Industry Analysis and Trends
3.09
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