Demonstration of Rapid Deuterium Annealing for High-Performance MOSFETs With Reduced Thermal Budget

As the critical dimensions of advanced CMOS devices continue to shrink, developing a novel forming gas annealing (FGA) process is essential for improving device yield and reliability. Traditional FGA processes, typically performed at high temperatures for 30 min or longer, are unsuitable for advanced devices below the sub-3-nm scale or manufacturing processes such as monolithic 3-D integration, where minimizing the thermal budget is crucial. In this context, rapid deuterium annealing (RDA), conducted at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$250~^{\circ }$</tex-math> </inline-formula>C for 3 min, is proposed to significantly reduce the thermal budget. The effectiveness of RDA was evaluated by fabricating silicon-based test MOSFETs and extracting device parameters.