Simulation Analysis and Optimization of Board-Level Power Integrity Based on PDN Impedance

As integrated circuit (IC) chips evolve toward high speed, high density, low voltage, and high current, ensuring power integrity (PI) has become increasingly prominent. Inadequate power integrity design can lead to deviations from the ideal performance even with more decoupling capacitors. This paper presents a design methodology for the selection and placement of decoupling capacitors based on target impedance, concentrating on the core aspect of power integrity: the power distribution network (PDN). The study began with analyses related to an equivalent model representing board-level capacitance, the decoupling effects of different capacitor combinations, and relevant optimization methods based on the full-band PDN composition. Subsequent investigation explored the influence of trace lengths, trace widths, and via hole intervals for capacitor placement on the parasitic inductance of circuits, in view of the impact of parasitic inductance introduced during the capacitor placement process on the decoupling effect of capacitors. Additionally, simulations were conducted to optimize PDN impedance based on real printed circuit boards (PCBs). The simulation results showed that the optimized PDN met the target impedance requirements, achieving a 15% reduction in the number of capacitors utilized, along with lowered cost, enhanced power integrity, and improved reliability of PCBs.