Memristors in an Integrated Circuit

A test chip with modules of non-volatile resistive memory containing a crossbar array of 32 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\times 8$</tex> memory cells “1 transistor – 1 memristor” is investigated. The memory cell is based on a thinfilm Au/Ta/ZrO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>(Y)/Pt/Ti structure integrated with a 0.35 μm complementary “metal-oxide-semiconductor” chip. The study was carried out using high-resolution transmission electron microscopy of the cross section and electrophysical characterization. The structure of the layers - Au, ZrO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> (Y), Pt, TiN and Ti (under the memristor) - polycrystalline; Ta - Amorphous. The Ti layer located in the memristor is an amorphous matrix with nanocrystalline inclusions. Memory cells demonstrate more than 5. 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> cycles of bipolar resistive switching, low switching energy <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\approx 17\text{nJ}$</tex>, stable and clearly distinguishable resistive (logical) states. An important feature of this cell from a practical point of view is the lack of electroforming requirements, which minimizes the voltage used. The developed approach and the research results provide a scientific and technological foundation for memristor applications in integrated circuit design for neuroelectronics and neuromorphic computing systems.