Tru-Sign: Lossless Truncated Sign Based Energy Efficient DNN Accelerator

In this paper, we present a lossless compression technique for DNNs, where the bit-widths of activations and weights are reduced by truncating sign extension bits. Based on the observations that consecutive activations or weights with small absolute values frequently appear in the layers of the DNNs, those activations and weights are compressed to reduce computational complexity as well as the number of memory accesses. We also present Tru-Sign hardware architecture, a DNN accelerator with a processing element that can seamlessly process the compressed activations and weights without accuracy loss. In the proposed approach, lossless acceleration has been achieved without any modification or retraining to the original DNN models. The proposed Tru-Sign has been designed and implemented using a 28nm CMOS process. The experimental results demonstrate improvements in energy efficiency and throughputs compared to numerous DNN accelerators.