FPGA Routing Algorithm Considering Maximum Delay Optimization

In a multi-FPGA prototype system, the Time Division Multiplexing (TDM) technique is applied to address the pin limitation issue for signal transmission. However, this approach introduces additional system delays, thereby reducing the system clock frequency. To mitigate this, we propose an FPGA routing algorithm that jointly optimizes the TDM ratio and maximum delay. The algorithm consists of three key strategies: (1) a routing-driven placement framework for large-scale heterogeneous FPGA, including partitioning, logic packaging, congestionaware global placement, legalization, and greedy refinement; (2) a Lagrangian relaxation-based initial TDM ratio assignment strategy, comprising problem transformation, dual decomposition, and subproblem solving; and (3) a practical TDM ratio legalization approach coupled with a history-aware negotiation-based maximum delay optimization technique to avoid local minima. Experimental results on ISPD2016 benchmarks demonstrate that the proposed method achieves up to 7.0 % reduction in delay after TDM ratio assignment, 13.4% reduction in maximum system delay after optimization, and 20.3% improvement in runtime for small-scale testcases, with average improvements of 2.1 %, 6.0 %, and 5.0 %, respectively. These results confirm the effectiveness of our algorithm in enhancing timing and runtime performance in TDM-based multi-FPGA systems.