The Computational-experimental Technique for Latchup Level Prediction in CMOS ICs Based on the Enlarged Parameters of the Diffuse and Drift Model

CMOS ICs (Integrated Circuits) are widely used as units of special-purpose electronic devices with special requirements for reliability and radiation hardness. Most of modern ICs (such as memory, microcontrollers and microcircuits of standard logics) are fabricated by CMOStechnology. The design of integrated circuits assumes 4 interlaced layers of n-p-n-p conductivity in the semiconductor structure. Under the pulsed gamma radiation one can observe such process as breaking down the electrical mode of CMOS ICs, that occurs the risk of transition of this structure to a lowimpedance state due to increasing of ionization currents in CMOS structure. This current can destruct the ICs metallization. This effect is known as “latchup effect”. In this work we demonstrate a new technique of prediction the latchup level in CMOS ICs using the enlarged parameters of diffuse and drift model under pulse radiation with random shape. This technique is using the experimental data for the ionization reaction prediction of diode structures for estimating the threshold levels of latchup of CMOS ICs.