Multi-Task Learning for Routability Prediction

The rapid development of Very-Large-Scale-Integration (VLSI) has raised challenges to the scalability and reliability of Electronic Design Automation. Early-stage routability prediction can significantly accelerate the design process by assessing routing congestion and Design Rule Check (DRC) violations. While machine learning has become the mainstream approach, existing studies often focus on task-specific models, overlooking the correlation between congestion and DR C violations, and lacking cross-task generalization. To address these limitations, this work proposes a unified framework that combines a U-Net architecture with multi-task learning, enhanced by residual networks and attention mechanisms. Using shared chip features, the framework simultaneously predicts congestion and DRC violations, significantly reducing prediction time. Experimental results on the CircuitNet dataset show that the proposed method achieves competitive performance across both tasks, demonstrating its capability in capturing complex physical design characteristics.