A 14-Bit 150 kS/s Hybrid Adc for Matrix Applications

This paper presents a novel 14-bit hybrid analog to digital converter operating at 150 kS/s in a 180 nm complementary metal oxide semiconductor process, optimized for low-power matrix readout systems such as bolometric sensor arrays. The proposed architecture integrates a successive approximation register and a slope-based converter to achieve 12.55 effective number of bits at a total power consumption of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$140 \mu ~\mathrm{W}$</tex>, with a compact core area of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.056 ~\text{mm}^{2}(34 \times 1640 \mu ~\mathrm{m})$</tex>. The conversion is partitioned into two stages: the first resolves the upper 5 bits using a capacitive digital to analog converter, while the residual voltage is amplified and digitized by a slope converter for the remaining 9 bits. A digital calibration technique mitigates inter-stage gain mismatches, ensuring linearity without post-processing overhead. Power efficiency is enhanced through dynamic block deactivation. Clock gating and time-shared resource allocation further minimize dynamic power dissipation. Designed for high-density integration, the converter supports multi-channel synchronization in matrix applications requiring moderate sampling rates and precision. This work advances hybrid analog to digital converter design, offering a scalable, energy-efficient solution for next-generation sensor interfaces in medical imaging, internet of things edge devices, and distributed sensing networks.