A Low-Power Analog Front-End for Photoplethysmography Signals with Dynamic Range Enhancement

This paper presents the design of an integrated low-power analog front-end (AFE) for photoplethysmography (PPG) signal acquisition with offset compensation based on dynamic range enhancement (DRE) technique, which can be used in wearable devices such as smartwatches, smart rings and other low-power systems. The PPG circuit can be divided in two parts: receiver and transmitter. The proposed receiver is implemented with a transimpedance amplifier (TIA) and a current-steering DAC (IDAC) controlled by a DRE circuit to compensate the current offset at the input node, followed by a low-pass filter designed using the gm-C topology, a programmable gain amplifier (PGA), and an output buffer. The DRE technique is also employed in the PGA circuit to control the saturation at the output node. On the transmitter side, an LED is used to emit light, controlled by a driver. The AFE was developed in 65 nm CMOS process with a supply voltage of 1.2 V. The IDAC can compensate up to $7 \mu \mathrm{~A}$ DC offset of the input current signal supplied by a photodiode. The system has an output voltage swing of about 700 mV PP with a DC voltage level of 600 mV and a low cut-off frequency of 724.53 Hz. The maximum power dissipation is $18.15 \mu \mathrm{~W}$ and the total silicon area is $363.65 \times 352.25 \mu \mathrm{~m}^{2}$.

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Publication Details

Published
2025-08-25
DOI
https://doi.org/10.1109/inscit66472.2025.11181034
Citations
1
Primary Topic
Forest Insect Ecology and Management
Type
article
Field-Weighted Citation Impact
1.72
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article

A Low-Power Analog Front-End for Photoplethysmography Signals with Dynamic Range Enhancement

1 citations
Forest Insect Ecology and Management
1.72
article

A Low-Power Analog Front-End for Photoplethysmography Signals with Dynamic Range Enhancement

article en
1 citations

Abstract

This paper presents the design of an integrated low-power analog front-end (AFE) for photoplethysmography (PPG) signal acquisition with offset compensation based on dynamic range enhancement (DRE) technique, which can be used in wearable devices such as smartwatches, smart rings and other low-power systems. The PPG circuit can be divided in two parts: receiver and transmitter. The proposed receiver is implemented with a transimpedance amplifier (TIA) and a current-steering DAC (IDAC) controlled by a DRE circuit to compensate the current offset at the input node, followed by a low-pass filter designed using the gm-C topology, a programmable gain amplifier (PGA), and an output buffer. The DRE technique is also employed in the PGA circuit to control the saturation at the output node. On the transmitter side, an LED is used to emit light, controlled by a driver. The AFE was developed in 65 nm CMOS process with a supply voltage of 1.2 V. The IDAC can compensate up to $7 \mu \mathrm{~A}$ DC offset of the input current signal supplied by a photodiode. The system has an output voltage swing of about 700 mV PP with a DC voltage level of 600 mV and a low cut-off frequency of 724.53 Hz. The maximum power dissipation is $18.15 \mu \mathrm{~W}$ and the total silicon area is $363.65 \times 352.25 \mu \mathrm{~m}^{2}$.

Universidade Federal do Pampa (BR)
Openalex Percentile: Top 11%
Forest Insect Ecology and Management
1.72
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