Digital Low-Latency High-Frequency Electrical Breakdown Detector and its Hardware Implementation

This paper presents a method and field-programmable gate array-based hardware implementation of a high-speed detector for electrical breakdown of high-frequency voltage. The method is based on envelope detection using the Hilbert transform. A distinguishing feature is the use of a second-order finite impulse response Hilbert filter with amplitude distortion compensation. As a result, a wide bandwidth was achieved, limited by the signal's spurious-free dynamic range. This method enables low-latency detection by eliminating the need for a low-pass filter, with the Hilbert transform introducing only a one-clock-cycle delay. A system with a sampling frequency of 250 MHz and a carrier frequency of 20 MHz, with a spurious-free dynamic range of 30 dB, where the dominant spurious component is located at the third harmonic of the carrier frequency, was chosen for hardware implementation. Simulation results indicated a detection latency of 20 ns from the onset to the completion of the electrical breakdown within the field-programmable gate array, with a signal fall time of 24 ns.

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Publication Details

Published
2025-06-27
DOI
https://doi.org/10.1109/edm65517.2025.11096637
Primary Topic
Trypanosoma species research and implications
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article
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Digital Low-Latency High-Frequency Electrical Breakdown Detector and its Hardware Implementation

Trypanosoma species research and implications
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Digital Low-Latency High-Frequency Electrical Breakdown Detector and its Hardware Implementation

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Abstract

This paper presents a method and field-programmable gate array-based hardware implementation of a high-speed detector for electrical breakdown of high-frequency voltage. The method is based on envelope detection using the Hilbert transform. A distinguishing feature is the use of a second-order finite impulse response Hilbert filter with amplitude distortion compensation. As a result, a wide bandwidth was achieved, limited by the signal's spurious-free dynamic range. This method enables low-latency detection by eliminating the need for a low-pass filter, with the Hilbert transform introducing only a one-clock-cycle delay. A system with a sampling frequency of 250 MHz and a carrier frequency of 20 MHz, with a spurious-free dynamic range of 30 dB, where the dominant spurious component is located at the third harmonic of the carrier frequency, was chosen for hardware implementation. Simulation results indicated a detection latency of 20 ns from the onset to the completion of the electrical breakdown within the field-programmable gate array, with a signal fall time of 24 ns.

Joint Institute for Nuclear Research (RU), Institute for Nuclear Research (RU)
Affordable and clean energy
Openalex Percentile: Top 38%
Trypanosoma species research and implications
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Digital Low-Latency High-Frequency Electrical Breakdown Detector and its Hardware Implementation · (2025) | TGRS Research Map | TGRS