Modeling of an Optimized Self-Aligned Selector Device for High-Density RRAM Arrays

The development of resistive random-access memory is of greatest importance for creating new class of memory in various applications, including large-scale memory arrays, analogue neuromorphic computing systems and energy-efficient system-on-chips. Filamentary switching mechanism of resistive memory provides great scalability and multilevel analogue switching, while non-volatility, energy efficiency, high retention and write/erase speeds make resistive memory a prospective universal memory. However, in Crossbar arrays advantages of resistive memory in scalability are limited by selector devices needed for preventing sneak path currents and providing correct write, read and erase operations. The reason behind this limitation is that the area of selector device exceeds the minimal possible area of memory cell. In this paper, we discuss the tunnel diode selector device with double layer dielectric which area is equal to that of the memory cell, or a self-aligned selector. The emphasis of our research is on theoretical modeling of electrophysical parameters of self-aligned selector optimized for Crossbar resistive memory arrays. The results presented in this paper are useful for enhancing the overall performance of resistive memory crossbar arrays for various applications, as well as for other areas where an optimal tunnel diode is required.