Hardware-Software Co-design Fault-tolerant Strategies for Systolic Array Accelerators

In recent years,with the continuous improvement in model inference accuracy,convolutional neural networks(CNNs) have been widely applied in safety-critical fields.To meet the demands of CNNs for real-time,high-performance,and low-power computing,domain-specific CNN accelerators is proposed.Among these,systolic array architectures have been extensively used due to their simple structure and high parallelism.However,factors such as process variations and equipment aging make systolic arrays prone to Stuck-At faults(SAF),which can lead to catastrophic accidents.Therefore,fault-tolerant strategies for systolic arrays are critically important.Existing fault-tolerant strategies,however,suffer from high time and resource costs,as well as excessive modifications to network parameters.To achieve an efficient and low-overhead lightweight fault-tolerant strategy,this paper aims to exploit the inherent fault tolerance of CNNs by relaxing the handling of minor SAFs,thereby reducing overall fault-tolerance overhead.Additionally,by fully considering the computational characteristics of systolic arrays,this paper proposes two hardware-software co-design fault-tolerant strategies:row(column) swapping and weight splitting.These strategies effectively mitigate the impact of SAF on model inference accuracy.Experimental results show that,compared to traditional row(column) bypass and selective protection strategies,the proposed hardware-software co-design fault-tolerant strategies offer superior execution efficiency and model accuracy recovery.