Energy-Efficient VLSI Ferroelectric Elements for Neuromorphic Artificial Intelligence Systems

Three-dimensional integration of double-gate transistors with full depletion in silicon-on-insulator structures and a high-k buried dielectric, in the form of so-called fin field effect transistors with two to four gates (gate-all-around) and nanowires, nanosheets, nanofork transistor channels, 2D materials and 3D cross-bar architecture made it possible to increase the number of transistors on a chip, but not their performance and energy consumption. The last one is crucial for ultra large scale integration chips for artificial intelligence. As a goal and a new ULSI platform, the option of decrease in the number of transistors and increase in their functionality is considered by replacing dielectrics under their gates with ferroelectrics and resistors with ferroelectric tunnel junctions, which provide low-voltage operations, and it leads to a transition from binary to neuromorphic logic, as well as to the implementation of the principles of radiophotonics, quantum devices and sensors with parallel processing. Dynamically adjustable threshold or ferroelectric capacity, resistors with ferroelectric tunnel junctions and a ferroelectric field effect transistor in a system-on-chip can reach ultra-low power consumption for Internet-of- Things.