Buried Power Rail Technology to Reduce Logic Gate Layout Designed on 7NM Open-Source PDK

In this article, we offer a solution to reduce the layout of digital standard cells on Fin Field-Effect Transistors for open-source Process Design Kit “ASAP7” due to the use of promising technology of buried power rails instead of a standard technological process. The domestic PDKs being developed in our country for technological nodes of 15 nm and below are extremely far from the technological design kits for production used in other countries, since there are no necessary technological and circuit models for nanotransistors and digital standard cells. On the other hand, the existing freely distributed means of automated very-large-scale integration design does not even support available educational Process Design Kits with Fin Field-Effect Transistor technology, therefore, the adaptation of existing computer-aided design systems that support new design methods and new Very-large-scale integration elements is necessary. Due to these factors, the open PDK “ASAP7” was chosen. After changing the layout of standard cells according to the buried power rail technology, we assessed the preliminary prospect at the level of structural synthesis on the new library with simplified models. We have simulated circuits from “ISCAS85” and “ISCAS89” test sets, and the results showed a significant decrease in the total area (maximum value of 25%) with a tendency to reduce leakage and total power (on average about 4–6% and insignificant worsening delays (on average less than 1%).