RSPE: A High Energy Efficient SNN Inference Processor with RISC-V based Dynamic Pruning Mechanism

In recent years, Spiking Neural Networks (SNN) have received increasing attention and application due to their low power consumption and good performance, especially for edge computing scenarios and SOC integrated design. This article introduces a RISC-V based SNN Processing Element (RSPE) based on 64-bit RISC-V, which embodies a RISC-V processor into SNN inference processors to support more flexible and comprehensive Dynamic pruning mechanism of SNNs. Three technical improvements are provided. Firstly, RSPE has a Pulse Dynamic Pruning Scheme (PDPS) that facilitates dynamic pruning across various dimensions using RISC-V instructions, thereby further decreasing computational complexity; Secondly, RSPE supports a Smart Computing based on Matching Mechanism (SCMM), realizing fast computation by storing and reproducing repeated calculations of SNNs based on the instruction stream; Thirdly, RSPE has a Flexible Intermediate Variable Transformation (FIVT), adjusting the computational data to a format more suitable for SNNs and RISC-V instruction set operations. The evaluation was conducted using a 28nm CMOS process, and the results showed that the RSPE achieved good performance.