Co-Optimization of Floorplanning and Decap Placement for TI and PI Based on Machine Learning

Power integrity (PI) and thermal integrity (TI) co-optimization in semiconductor packages is challenging due to floorplanning and decap placement trade-offs. This paper proposes a reinforcement learning (RL)-based floorplanning method that optimizes PI and TI while considering decapinduced PDN resistance. Using a thermal resistance matrix, our method achieves <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$500 \times$</tex> faster thermal analysis than computational fluid dynamics (CFD) solvers with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$&lt;2 \%$</tex> error. Simulation results show 22.8 % and 19.4 % improvement over single-metric optimization, based on evaluations of 250 floorplans and 4 decap status variations, ensuring thermal performance and voltage stability. This framework provides a scalable solution for next-generation semiconductor packages.