Multilevel Voltage Source Inverters with Improved Selective Harmonic Elimination Using a PAM-PWM Control Topology

Power inverters are extensively employed in a wide range of applications such as VSD, PV, UPS, and Vehicle-to-Grid systems. Different control topologies are used in power electronic inverters. Of these, PWM and MLVSIs are implemented to minimize the harmonic contents of the generated waveforms, as well as to minimize the complexity and cost of these systems. Although PWM inverters offer an acceptable waveform quality, the switching losses of the power elements is considered a major drawback. MLVSIs provide excellent waveform quality at reasonable switching losses, but at the expense of a relatively higher cost and design complexity. However, when applied to constant voltage constant frequency applications such as PV, UPS, and Vehicle-to-Grid systems, the cost and design complexity become reasonable. In this paper, a generalized analytical analysis and solution of an M-Stage MLVSI with a certain selective harmonic elimination (SHE) control topology is reported. This leads to completely eliminate certain lower-order harmonics of the generated waveforms. The number of harmonics that can be eliminated depends upon the number of the system DC link stages. The results show that as the number of stages increases, a significant improvement of the waveform quality is achieved. However, the tendency of this quality to further improve as the number of stages increases is remarkably reduced.