A SRAM-Based In-Memory Accelerator Featuring Complete SAT Solving and CAM Operations for Efficient Network Transmission

Boolean Satisfiability (SAT) based verification and Content Addressable Memory (CAM) based lookup operations contribute to the efficiency of network packet transmission. Although related In Memory Accelerators (IMAs) provide substantial computational acceleration, current implementations still face limitations: IMAs based on incomplete SAT-solving methods are unsuitable for verification tasks; IMAs that integrate verification and lookup functionality are rare. To overcome these limitations, we propose an IMA based on Static Random-Access Memory (SRAM) that integrates both complete SAT-solving capabilities and high-throughput lookup operations. In this work, clause satisfiability determination and backtracking operations are implemented for complete SAT solving. Meanwhile, the RWL-split 11T SRAM array with 144Kb capacity increased the throughput of CAM based lookup operations. The prototype has been fabricated using a 65nm process. The power consumption of approximately 19.3mW under a supply voltage of 1.1V and a working frequency of 100MHz. The experimental results are demonstrated. For solving SAT problems, this work achieves 100% solvability in the SATLIB benchmark. For lookup operations, it consumes 0.13 fJ/search/bit and 0.26 fJ/search/bit for binary and ternary CAM operations, respectively.