Design and Implementation of a Novel 64-Bit Hybrid Ling Adder Using RCA, CLA

High-speed arithmetic operations are essential for modern computing systems, particularly in applications requiring low-latency addition and optimized power efficiency. Traditional adders, such as Ripple Carry Adders (RCA) and Carry Look a- head Adders(CLA),each have inherent trade-offs between speed, area, and power consumption. This paper presents the designand implementation of a novel 64-bit Hybrid Ling Adder, which strategically combines RCA and CLA architectures to enhance computational efficiency. The proposed hybrid adder leverages Ling’s transformation to optimize carry propagation, reducing critical path delay while maintaining hardware simplicity. The lower significant bits utilize a Ripple Carry Adder for area efficiency, whereas the higher significant bits implement a Carry Lookahead Adder to accelerate carry computation. This hybridization achieves an optimal balance between delay reduction and resource utilization, making it suitable for high-performance arithmetic circuits. The Verilog implementation of the 64-bit Hybrid Ling Adder was synthesized and simulated using Xilinx Vivado, demonstrating improved delay performance compared to conventional RCA and CLA architectures. Experimental results indicate that the proposed design achieves significant speedup with reduced logic complexity, making it a promising candidate for next-generation arithmetic units in processors and DSP applications.