Multi-corner optimization of RSFQ circuits for test yield improvement

Abstract Rapid single flux quantum (RSFQ) circuits are a promising technology for the post-Moore’s law era. However, large-scale RSFQ circuits still suffer from low test yields. One major reason for the low test yield is the instability of process parameters, which can cause variations in the internal parameters of SFQ circuits, thereby leading to functional errors. Although some research teams have attempted to address parameter fluctuations from a design perspective or through process improvements to mitigate their impact, the lack of integration between design optimizations and process enhancements has resulted in still unsatisfactory test yields. This study proposes and validates a specific and practical multi-corner optimization design flow for RSFQ circuits to establish a positive feedback mechanism between process and chip design. This design flow enables the incorporation of process parameter variations at the design stage, thereby ensuring the circuit achieves expected performance. After fabrication, the predefined process corners can be used to quickly determine whether the chip batch falls within the testable range, while actual process information is continuously fed back to the design end for iterative optimization. To validate this flow, we performed a statistical analysis of process control monitor parameters from multiple batches of the SIMIT Nb03 process, identifying the corresponding process corners suitable for circuit design. Using this flow, we first optimized cell parameters to ensure sufficient bias margins across different corners, improving cells’ robustness for large-scale circuits. We then designed a full adder and an auxiliary test circuit using this design flow and achieved 100% test yield with test results perfectly matching simulation results. Meanwhile, a pattern-matching circuit not using multi-corner optimization method demonstrated a counterexample with low test yield. Finally, we established digital models using timing parameters across different process corners to enhance the reliability of large-scale RSFQ circuit design.