Memory Separation Method for High-Level Synthesis of Lenet5

In this paper, we propose a new memory separation method to improve the operating speed when implementing LeNet5, a representative convolutional neural network, on an FPGA (field programmable gate array) using an HLS (high-level synthesis) tool.The implementation method using HLS has the advantage of a short development period because it implements an FPGA using codes written in general software languages such as C and C++.On the other hand, compared to the implementation method using HDL (hardware description language), there are fewer ways for users to optimize the implementation.In this paper, we analyze the existing HLS implementation method and show that there is a problem in that the number of operations is not optimized when the execution statement in the loop requires multiple operation clocks.In addition, to solve this problem, we propose a new method in which one memory is divided into two memories with half the capacity so that the execution statement in the loop operates in a single clock.In addition, we propose a method in which the next step is calculated using the two separated memories.The method proposed in this paper is implemented using Xilinx Vitis HLS and compared with existing methods in terms of operating speed and FPGA resource usage, and it is shown that the proposed method is superior to methods using HLS in operating speed.