Efficient Optimization Techniques for Subthreshold Leakage Reduction in Nano Domino Circuits Using ONOFIC with FinFET and CNTFET Technologies.

Energy efficiency is a critical concern in modern nano-scale VLSI systems, especially for battery-powered and portable electronic devices. This study introduces a novel design approach for low-leakage domino logic circuits using FinFET and CNTFET technologies at the 32nm technology node. The goal is to significantly reduce subthreshold leakage power while maintaining high performance and area efficiency. Four innovative circuit architectures based on the ONOFIC (ON/OFF Isolation Control) technique are proposed: (i) ONOFIC Pull-Down, (ii) Dual-ONOFIC Pull-Down, (iii) ONOFIC Pull-Up, and (iv) Sandwiched ONOFIC structure. These architectures strategically isolate dynamic nodes from the evaluation network to minimize leakage during idle states. In addition, dual-chirality CNTFET designs and LECTOR-based implementations are explored for comparative analysis. All circuits are simulated using HSPICE, with a focus on wide OR gates, extended to functional units like multiplexers. The results indicate that the ONOFIC Pull-Up architecture achieves the most significant leakage reduction, providing a 21.9% improvement over conventional footer-less domino logic and a 69.5% reduction compared to LECTOR-based domino circuits. The proposed nano-domino circuits offer a scalable, energy-efficient solution suitable for advanced digital systems, including IoT edge devices and low-power processors.