DESIGN AND ANALYSIS OF SPIN-BASED LOGIC GATES FOR ENHANCING COMPUTATIONAL EFFICIENCY

Spin transistors (Spin-FETs) are a promising way to solve problems with non-volatility, speed, and power consumption in standard CMOS technology. The Spin-FET electrical model using InAs channel material with 800 nm and 820 nm channel lengths is briefly explained in this paper. Spin-FET local geometry can be used to execute digital logic functions according to the experimental analysis. The local geometry of the spin transistor is designed using the Datta-Das concept and the spin injection and detection theory. It is implemented using the Verilog-A language on a Cadence platform. Transient and DC analysis for various channel lengths have been used to validate the results. The power consumption and capacitance of the complementary spin-FET and conventional CMOS have also been compared. This permits the inverter and buffer gate to function with a complimentary spin-transistor. In contrast to other research, our study presents XNOR and XOR gates that are built using a single gate SFET control input technique. However, our design improves computational efficiency by using a novel technique to regulate spin-based logic gates.