A 50-kHz BW, 84.6-dB SNDR Noise-Shaping SAR ADC With Capacitor-Mismatch-Error-Free Switching Scheme

This brief presents a noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) for biomedical Internet-of-Things (IoT) applications. The proposed capacitor-mismatch-error-free (CMEF) switching scheme intrinsically eliminates MSB digital-to-analog converter (DAC) mismatch errors through identical shift in the bottom-plate reference voltage, thereby realizing 0.9- and 2.9-dB improvements in the signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR), respectively, over the tri-level switching method. Fabricated in a 40-nm CMOS technology, the prototype NS-SAR ADC occupies a core area of 0.053 mm<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}^{\mathbf {2}}$</tex-math> </inline-formula> and consumes <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$87.7~\mu $</tex-math> </inline-formula>W at 1.1-V supply. With an oversampling ratio (OSR) of 12 and a 50-kHz bandwidth (BW), it achieves 84.6-dB SNDR and 95.4-dB SFDR, yielding a Schreier figure-of-merit (FoM) of 172.2 dB and a Walden FoM of 63.2 fJ/step.