HYBRID TYPE ERROR CORRECTION CODE TO INCREASE RELIABILITY IN SRAM MEMORIES

This paper presents implementation of mixed mode Error Correction Coder architecture that is capable of detecting and correcting both random and burst. The proposed architecture executes two different types of architectures in which one of them aims at targeting the random while the other aims at burst. The diagnosis of random faults is obtained by employing the modified decimal matrix coding whereas the burst diagnosis is done by flexible unequal error method. The proposed architecture gains an adequate advantage with respect to area overhead and power consumption. The proposed architecture is implemented in cadence. In the front end design the parameters are estimated by using out by GENUS and on similar lines, the back end design is carried out by using out by INNOVUS and the performance metric generated includes Area Report, Power Report, and timing report and chip layout. The area, power and delay overhead of the proposed architecture is found to be 50088.491, 20.7mW and 2.11ps which are very small compared to other ECC that are taken for experimental purpose and this low values of area, power and delay are mainly due to the use of encoder reuse technique. Further the experimental results conclude fact that the proposed architecture can achieve 100% of error correction up to six bits and offers correction rate of 80.76 and 68.43 for burst of length 7 and 8 respectively. The error correction capabilities for random error is found to be 100% for Quintuple Bit Error and there after we observed slight decrement in error correction capability for Sextuple Bit, Septuple bit and Octuple Bit. The percentage of error correction rate for Sextuple bit, Septuple bit and Octuple bit is found to be 46, 4 and 2 respectively. The increased reliability of this hybrid type error correction code is achieved at a cost of slight increment in the overhead bits.