A 14.5-mW 10-GS/s 16× Time-Interleaved 7-bit SAR ADC With Low-Power Ring Amplifier Buffers

This article investigates a 10-GS/s 7-bit successive approximation register (SAR) analog-to-digital converter (ADC) with an extremely low power consumption of 14.5-mW using low-power ring amplifiers as buffer in the track-and-hold stage. It is implemented in a 22-nm fully depleted silicon-on-insulator (FD-SOI) technology. This feasibility study is based on 16 time-interleaved loop-unrolled SAR ADC cores utilizing subsampling with a division factor of four for both stages. Since this sampling strategy requires a buffer, different suitable topologies are considered and compared to each other, and it is concluded that the ring amplifier offers the best capabilities in terms of gain, bandwidth, and power consumption. It consists of three inverters and is used here in a switched-capacitor feedback configuration with a voltage gain of 3.5 dB. Its bandwidth exceeds 20 GHz while it consumes only 1.2 mW demonstrating the potential of this amplifier concept in ultralow-power high-speed ADCs. Within the clock tree, a phase correction unit is implemented, which is able to shift the subclocks after the first division in a range of 10 ps. This is achieved by controlling the backgate voltage of an inverter chain and switching additional capacitors to load or unload the internal nodes. Additionally, the gain of each ADC core can be tuned allowing for a very good adjustment of the cores. For this purpose, a digital calibration routine is implemented. Layout aspects are also taken into account and the whole design was optimized for low power consumption. For optimized settings, the signal-to-noise-and-distortion ratio (SNDR) is well above 30 dB for an input frequency of 4.7 GHz, which is close to the Nyquist limit. The power consumption is as low as 14.5 mW for a supply voltage of 0.72 V, which is, to the best of the authors’ knowledge, the lowest reported value for beyond-5-GS/s ADCs today. The respective Walden figure of merit (FoM<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> _W </i>) is 41.6 fJ/conv.step and the Schreier figure of merit (FoM<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> _S </i>) is 147.8 dB. Even in undersampling scenarios with input signals up to approximately 10 GHz sampled with 10 GS/s (second Nyquist zone), the measured SNDR remains above 20 dB. The maximum absolute values of integral nonlinearity (INL) and differential nonlinearity (DNL) are 0.62 LSB and 0.61 LSB, respectively.