On-Current Degradation in Ultra-Scaled Nanosheet FETs With S/D Underlap Doping

Aggressive gate pitch scaling makes it increasingly challenging to control the doping gradient at the source/drain (S/D) extensions. To address this, S/D underlap doping has been proposed as a solution. However, anomalous I<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D,lin</sub> saturation has been experimentally observed in such devices, raising questions about its physical origin. In this work, we investigate the transport physics in ultra-scaled nanosheet FETs by solving the Subband Boltzmann Transport Equation. The simulation results reveal that secondary barriers formed in underdoped S/D extensions enhance quasi-ballistic transport even in the linear regime, providing a consistent explanation for the observed I<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D,lin</sub> saturation in underlap devices. These insights offer guidance for optimizing S/D underlap doping profiles, highlighting the need to avoid excessive Gate-S/D overlap capacitance while preventing on-current degradation.