Clean and Uniform High- <i>k</i> Gate Dielectric Integration for 2-D Field-Effect Transistors

Two-dimensional (2-D) semiconductors offer a pathway to extend Moore’s law beyond silicon’s fundamental limits, leveraging their atomic-scale thickness and inherent immunity to short-channel effects. However, integrating high-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$k$</tex-math> </inline-formula> gate dielectrics with 2-D semiconductors presents unique hurdles. The dangling-bond-free surface of 2-D semiconductors impedes uniform high-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$k$</tex-math> </inline-formula> dielectric growth; their atomically thin thickness amplifies sensitivity to surface/interface defects, necessitating defect-minimizing integration processes. This work comprehensively analyzes the critical challenges and recent advancements in achieving high-quality gate dielectric–semiconductor interfaces for 2-D transistors, which are essential for their integration into scalable, energy-efficient integrated circuits. We systematically classify and benchmark four state-of-the-art integration strategies. Notable advancements include ultralow interface state density <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${D}_{\text {it}} \sim 10^{{9}}$</tex-math> </inline-formula> cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> eV<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> achieved by damage-minimizing techniques such as mechanical transfer. However, device-to-device nonuniformity remains a key challenge, with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${D}_{\text {it}}$</tex-math> </inline-formula> varying by up to three orders of magnitude. To advance interface engineering, we emphasize the need to characterize correlations among integration processes, defect formation, and device performance—critical for guiding defect-minimizing process design. In addition, evaluating technologies against rigorous standards for large-scale uniformity (e.g., wafer-level deposition) and cost-effectiveness (e.g., compatibility with CMOS infrastructure) is essential for transitioning 2-D transistors from laboratory prototypes to industrial manufacturing.