Efficient Extraction and Packing Modules for Posit Multipliers

This brief presents novel optimizations of the extraction and packing modules in posit arithmetic units. In the extraction module, a customized leading zero/one anticipator (LZA/LOA) is integrated with the incrementer to parallelize the 2’s complement operation and leading zero/one detection, which in turn reduces the critical path delay. The packing module is streamlined by merging two operations into a single incrementer step, leading to more compact hardware. To further improve the power efficiency, the output signals of the extraction module are synchronized using latches, effectively suppressing glitch propagation. Based on the proposed extraction and packing modules, 8-bit and 16-bit posit multipliers are implemented in TSMC 45nm technology. Post-layout results show that the proposed posit multipliers achieve up to 46.14%–52.18% reduction in power–delay product (PDP) compared with state-of-the-art designs.