Residual Stress in Multilayer NTC Thermistors during Bending Test

The stress occurred on the NTC (negative temperature coefficient) thermistor chip while serving process of the chip was investigated in this study. We built 3D models of NTCs and examined the stresses in chip inside with varying structures, on varying load conditions; structural bending load, temperature cycling load, separately and both. In the resistor ceramic body around termination regions which were connected with solders, the stresses had relatively significant values than the other regions and it was considered as a main factor of the failure of NTC body. When the number of the inner-electrodes increased, the maximum principle stress occurred on the inside of NTC was decreased gradually and when the number of electrodes was equal to 24, it had the lowest value as 524 MPa. Also, the stress changes of inside on varying times were investigated when the periodic temperature of the chip body was changed from -60 ℃ to 120 ℃. In this case, the maximum principle stress had the lowest value as 538 MPa also when the number of inner-electrode was also equal to 24. In addition, stress distribution patterns of bending load were compared with temperature cycling load. Through this study optimized geometry and failure condition of NTC were obtained.