Novel Hybrid SRAM for Low-Power Application

In this study, we experimentally demonstrate a hybrid static random-access memory (SRAM) cell that integrates both tunnel field-effect transistors (TFETs) and metal-oxide-semiconductor FETs (MOSFETs) for low-power applications. N-type MOSFETs are used as access and pull-down transistors to ensure stable read/write operations and to facilitate cell ratio tuning. For the pull-up transistor, pocket doping drain underlap (PDDU) TFETs are adopted to reduce power consumption. The fabricated hybrid SRAM successfully performs read and write operations, achieving an ~80.6% reduction in standby power consumption compared to a conventional SRAM with an identical layout. The device performance is further optimized through calibration between measured data and technology computer-aided design (TCAD) simulation. As a result, reliable read/write operations are demonstrated at 0.3 V-supply voltage, highlighting the potential of the hybrid SRAM for low-power applications.