Design and Performance Analysis of Solid State Fractional Capacitor‐Based Trans‐Receiver System

ABSTRACT The fractional‐order system modeling can better handle the complex dynamics and intricate properties of a real‐time system because of its more degrees of freedom. Thus, if stability is guaranteed, a synthesized fractional‐order system performs better than its integer‐order counterpart. In this paper, a fractional‐order trans‐receiver system has been designed using a solid‐state fractional capacitor to obtain superior performances. The proposed design overcomes the problems present in the ladder‐based fractional elements. A mathematical model of the trans‐receiver system has been derived in fractional‐order framework, and the proposed system is implemented in hardware. The experimental results of the integer‐ and fractional‐order systems have been compared in terms of SNR, noise, transmitted power, and jitter for low‐frequency operations. It has been shown that the developed device is more noise‐inhibitory and thus can be used for practical applications.