QtNURAV: A Robust Latch Design With Quintuple Node Upset Recovery and Algorithm Based Verifications for Aerospace Applications

With the continuous scaling of transistor feature sizes to the deep nano-scale, modern circuits have become increasingly sensitive to radiation-induced soft errors, such as multiple node upset (MNU). Especially, due to charge-sharing, the striking of one high-energy radiative particle can simultaneously impact multiple adjacent nodes of a highly integrated circuit causing MNU, e.g., quintuple node upset (QtNU) and even more node upsets. Existing MNU-hardened latch designs cannot provide QtNU recovery, and their robustness verification heavily depends on electronic-design-automation tools. In this paper, we present a robust latch, namely QtNURAV, to protect against QtNU for aerospace applications, along with an algorithm-based QtNU recovery verification method. The latch mainly employs four parallel dual-interlocked cells (DICEs) that feed each other through eight 3-input inverters to robustly retain values. The proposed algorithm simplifies the fault-tolerance verification process, demonstrating the QtNU recovery of QtNURAV. Simulation results based on HSPICE show that the QtNURAV latch can self-recover from any possible QtNU and has low delay and power consumption. Compared to existing Quadruple Node Upset hardened latches, the proposed QtNURAV latch provides QtNU recovery and effectively reduces delay, power and delay-power-area comprehensive product by 33.3%, 30.1%, and 53.3% on average, respectively.