Greedy Test Pattern Generation for Detecting Faults Using SAT in Locked circuits

Achieving high fault coverage is also crucial for reducing manufacturing defects. This greedy test pattern generation generates test pattern with minimum set of test pattern count that is capable of detecting all the faults with reduced testing time. In this the existing methodology is logic locking where we insert a logic gate at various locations of the logic circuit with the keys attached to them. By enabling correct keys only, the operation operates correctly. Here by applying SAT (Boolean Satisfiability) attack we can detect the fault in the circuit. SAT based ATPG is used to identify faults in digital circuits. SAT solver finds test pattern effectively to detect the fault. The existing method consists of two approaches the first approach is to generate one test pattern per fault and the second approach is to generate test pattern for a group of faults. We mainly targeted on Stuck – at faults. We propose greedy test pattern generation, So it is used in Automatic test pattern generation it is particularly used for digital circuits testing and fault detection capability. This greedy test pattern generation focuses on generating a minimal set of test vectors that can detect maximum number of faults. This greedy test pattern generation algorithm consists of the several steps, the first step is fault list initialization, the second step focuses on generating a pool of patterns, the third step is fault simulation, and the fourth step is greedy selection. Here we demonstrate that our method can achieve 100% fault coverage and the efficacy of this methodology can be shown on ITC’ 99 benchmarks circuits. These ITC 99 (International Test Conference 1999) benchmark circuits are set of standardized digital circuits that are used for evaluating test pattern generation. Additionally, we observe significant test generation time savings in the proposed in the second approach, as analysing multiple faults together helps reduce computational conflicts.

Publication Details

Journal
Tuijin Jishu/Journal of Propulsion Technology
Published
2025-04-08
DOI
https://doi.org/10.52783/tjjpt.v46.i02.9548
Primary Topic
Geochemistry and Geologic Mapping
Type
article
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article

Greedy Test Pattern Generation for Detecting Faults Using SAT in Locked circuits

Tuijin Jishu/Journal of Propulsion Technology
Geochemistry and Geologic Mapping
article

Greedy Test Pattern Generation for Detecting Faults Using SAT in Locked circuits

article en

Abstract

Achieving high fault coverage is also crucial for reducing manufacturing defects. This greedy test pattern generation generates test pattern with minimum set of test pattern count that is capable of detecting all the faults with reduced testing time. In this the existing methodology is logic locking where we insert a logic gate at various locations of the logic circuit with the keys attached to them. By enabling correct keys only, the operation operates correctly. Here by applying SAT (Boolean Satisfiability) attack we can detect the fault in the circuit. SAT based ATPG is used to identify faults in digital circuits. SAT solver finds test pattern effectively to detect the fault. The existing method consists of two approaches the first approach is to generate one test pattern per fault and the second approach is to generate test pattern for a group of faults. We mainly targeted on Stuck – at faults. We propose greedy test pattern generation, So it is used in Automatic test pattern generation it is particularly used for digital circuits testing and fault detection capability. This greedy test pattern generation focuses on generating a minimal set of test vectors that can detect maximum number of faults. This greedy test pattern generation algorithm consists of the several steps, the first step is fault list initialization, the second step focuses on generating a pool of patterns, the third step is fault simulation, and the fourth step is greedy selection. Here we demonstrate that our method can achieve 100% fault coverage and the efficacy of this methodology can be shown on ITC’ 99 benchmarks circuits. These ITC 99 (International Test Conference 1999) benchmark circuits are set of standardized digital circuits that are used for evaluating test pattern generation. Additionally, we observe significant test generation time savings in the proposed in the second approach, as analysing multiple faults together helps reduce computational conflicts.

Tuijin Jishu/Journal of Propulsion TechnologyVol. 46(02)
Openalex Percentile: Top 31%
Geochemistry and Geologic Mapping
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Greedy Test Pattern Generation for Detecting Faults Using SAT in Locked circuits · Tuijin Jishu/Journal of Propulsion Technology (2025) | TGRS Research Map | TGRS