Encoding Time Series on an FPGA, with an Efficient Izhikevich Neuron Implementation

Neuromorphic processing is a low power technique that can be used to process different types of data, including time series. ASICs are expensive and custom neuromorphic ICs are not yet widely available, such that another method needs to be considered, to speed up neuromorphic execution in hardware. This paper presents a spike encoding method using an FPGA, a readily available existing technology that can be wielded to process time series data. This approach efficiently encodes and decodes time series data and interfaces into a single layer of Izhikevich neurons. The technique we propose implements a low power and small FPGA design that responds to fast and dynamically changing chaotic time series input with low loss in the encoder and decoder. We explore the differing dynamics of the Izhikevich neuron and the effects on the error of the reconstructed time series data, proposing a set of constraints to minimise the error. Furthermore we investigate the number of neurons required to have an accurate spiking representation of the input with minimum loss.