ENERGY EFFICIENT COMPACT APPROXIMATE MULTIPLIER FOR ERROR RESILIENT APPLICATION

Improving system performance, including speed, form factor, and energy economy, is the main objective of approximation computing. Even while approximate multipliers are becoming more and more popular, designing effective approximation compressors, a basic multiplier block, is still quite difficult. Eighttransistor and fourteen-transistor 4:2 compressors are suggested in this short. With fewer negative errors, both compressors take use of CMOS technology and a constant and conditional approximation of specific inputs. Consequently, a resource-intensive error recovery module is removed, resulting in better performance than previous work. By sacrificing less size for more precision, the 14-transistor architecture produces a lower error rate than the 8-transistor architecture. Using image multiplication, the compressor's customized circuit design is also suggested and assessed. In comparison to the precise multiplier, the suggested multiplier shows superior accuracy, 38% PDP improvement, 50% area savings, and a 93% reduction in power-delay-product.