ZuSE-KI-Mobil: AI Chip Design Platform for Automotive and Industrial Applications

The ZuSE-KI-Mobil (ZuKIMo) research project presents a heterogeneous system-on-chip (SoC) designed for use in a variety of automotive and industrial edge applications. Implemented using GlobalFoundries (GF) 22-nm FD-SOI technology, the SoC features a modular architecture with a configurable, bit-serial, mixed-precision neural processing unit (NPU) core. This core can be adapted to different use cases, comes with a compact instruction set, and improves the performance of dilated convolutions. A hardware-accelerated, tunable image signal processor (ISP) hyperparameter pipeline reduces tuning time and increases detection confidence for AI tasks. The system also incorporates a selective, per-layer fault-tolerance mechanism and supports rapid prototyping via an Apache TVM-driven compiler flow and cycle-accurate simulation. The adaptable hardware generation process is designed with future chiplet-based scaling in mind, providing a flexible foundation for upcoming heterogeneous SoC designs.

Institutions

Publication Details

Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Published
2025-09-12
DOI
https://doi.org/10.1109/tvlsi.2025.3603887
Citations
1
Primary Topic
Geochemistry and Geologic Mapping
Type
article
Field-Weighted Citation Impact
2.48
Controls
|||
ALL TIME
JAN
FEB
MAR
APR
MAY
JUN
JUL
AUG
SEP
OCT
article

ZuSE-KI-Mobil: AI Chip Design Platform for Automotive and Industrial Applications

1 citations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Geochemistry and Geologic Mapping
2.48
article

ZuSE-KI-Mobil: AI Chip Design Platform for Automotive and Industrial Applications

article en
1 citations

Abstract

The ZuSE-KI-Mobil (ZuKIMo) research project presents a heterogeneous system-on-chip (SoC) designed for use in a variety of automotive and industrial edge applications. Implemented using GlobalFoundries (GF) 22-nm FD-SOI technology, the SoC features a modular architecture with a configurable, bit-serial, mixed-precision neural processing unit (NPU) core. This core can be adapted to different use cases, comes with a compact instruction set, and improves the performance of dilated convolutions. A hardware-accelerated, tunable image signal processor (ISP) hyperparameter pipeline reduces tuning time and increases detection confidence for AI tasks. The system also incorporates a selective, per-layer fault-tolerance mechanism and supports rapid prototyping via an Apache TVM-driven compiler flow and cycle-accurate simulation. The adaptable hardware generation process is designed with future chiplet-based scaling in mind, providing a flexible foundation for upcoming heterogeneous SoC designs.

IEEE Transactions on Very Large Scale Integration (VLSI) SystemsVol. 33(11)
Karlsruhe Institute of Technology (DE), Leibniz University Hannover (DE), BMW (Germany) (DE), Infineon Technologies (Germany) (DE), Vodafone (Germany) (DE), Leibniz University of Applied Sciences (DE), L3S Research Center (DE), Technical University of Munich (DE), Technische Universität Dresden (DE)
Industry, innovation and infrastructure
Openalex Percentile: Top 7%
Geochemistry and Geologic Mapping
2.48
AI Navigator

Ask Laika to Summarize, Analyze, and Connect papers live on the map.

Summarize Papers & Methodologies

Extract key findings, datasets, and comparative methods across publications.

Benchmark Rankings & Visual Analytics

Rank top research institutions, authors, funders, topics, and journals by Field-Weighted Citation Impact (FWCI) and paper volume with instant charts.

Connect Distant Disciplines

Bridge topological clusters on the map to find hidden collaborative intersections.

ZuSE-KI-Mobil: AI Chip Design Platform for Automotive and Industrial Applications · IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2025) | TGRS Research Map | TGRS