Warpage Optimization for SiC MOSFET Multichip Fan-Out Panel-Level Packaging With Thermal–Mechanical Finite-Difference Numerical Modeling and In Situ Digital Image Correlation Validation

Fan-out panel-level package has become a trend in silicon carbide <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> packaging due to its superior electrothermal performance and cost-effectiveness. However, the increased size of multichip embedded fan-out panel-level packaging (FOPLP) introduces greater challenges in sample preparation and thermal–mechanical stresses. In this article, a large-sized (20 mm*20 mm*0.78 mm) FOPLP with four SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small>s embedded is investigated. A 3-D thermal–mechanical numerical model is derived based on heat conduction and elasticity theories. It utilized analytical solutions of Fourier temperature conduction and finite-difference results for thermoelastic models to describe the temperature and deformation distribution during the FOPLP operation. It also reveals the heat-coupling issue of multiple chips. Compared with the finite-element simulation, the proposed method shows less than 2.5% error in temperature and 2.3% error in deformation. The computational speed is one-tenth that of the finite-element method, while the memory usage is reduced to one-fifth. To mitigate the influence of chip thermal coupling on temperature and warpage, an optimized layout was employed to achieve temperature uniformity improvement. Finally, FOPLPs with the two layouts were fabricated. The warpage was monitored using a digital image correlation platform. To achieve the same temperature, the current required for the optimized layout was increased by 9% . The warpage of the optimized layout at 60 °C was reduced by 13.5%, and at 100 °C, it was reduced by 14.7%, validating the accuracy of the model and the significance of thermal decoupling.