A Joint Data Transmission Scheme With Improved CAC for 3D-SICs Based on Multiple TSV Subarrays

Through-silicon via (TSV) is one of the key components enabling vertical electrical interconnects in three-dimensional (3D) stacked integrated circuits (SICs). The high density of TSVs poses substantial crosstalk challenges due to the coupling effects. Traditional Crosstalk Avoidance Codes (CACs) mitigate the crosstalk, whereas bring substantial codec area. The crosstalk suppression capability of CACs is also degraded by the edge effects of TSV array. Although the existing bus partition methods alleviate the drastic codec area increase of CACs, they result in higher bit overhead because the data to be transmitted by each sub-array is encoded independently. This work proposes the joint data transmission (JDT) scheme, in which the data to be transmitted by multiple TSV sub-arrays is encoded jointly. It is proved that the bit overhead of the JDT scheme is less than that of the independent data transmission (IDT) scheme. A systematic design method is proposed to optimize the sub-array parameters to minimize the total area of the codecs and TSVs. Furthermore, a new CAC technique named Exhaustive Reduced Adjacent Transition CAC (ERAT-CAC) is proposed to improve the crosstalk suppression capability under the edge effects by constraining adjacent signal transitions. Simulation results show that the proposed JDT scheme with the ERAT-CAC has better crosstalk suppression capability under the edge effect compared with FNS-FPF-CAC, FNS-FTF-CAC and 3D-DPS-CAC, along with smaller area overhead and lower transmission power.

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Publication Details

Journal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Published
2025-09-08
DOI
https://doi.org/10.1109/tcad.2025.3607139
Primary Topic
Geochemistry and Geologic Mapping
Type
article
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article

A Joint Data Transmission Scheme With Improved CAC for 3D-SICs Based on Multiple TSV Subarrays

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Geochemistry and Geologic Mapping
article

A Joint Data Transmission Scheme With Improved CAC for 3D-SICs Based on Multiple TSV Subarrays

article en

Abstract

Through-silicon via (TSV) is one of the key components enabling vertical electrical interconnects in three-dimensional (3D) stacked integrated circuits (SICs). The high density of TSVs poses substantial crosstalk challenges due to the coupling effects. Traditional Crosstalk Avoidance Codes (CACs) mitigate the crosstalk, whereas bring substantial codec area. The crosstalk suppression capability of CACs is also degraded by the edge effects of TSV array. Although the existing bus partition methods alleviate the drastic codec area increase of CACs, they result in higher bit overhead because the data to be transmitted by each sub-array is encoded independently. This work proposes the joint data transmission (JDT) scheme, in which the data to be transmitted by multiple TSV sub-arrays is encoded jointly. It is proved that the bit overhead of the JDT scheme is less than that of the independent data transmission (IDT) scheme. A systematic design method is proposed to optimize the sub-array parameters to minimize the total area of the codecs and TSVs. Furthermore, a new CAC technique named Exhaustive Reduced Adjacent Transition CAC (ERAT-CAC) is proposed to improve the crosstalk suppression capability under the edge effects by constraining adjacent signal transitions. Simulation results show that the proposed JDT scheme with the ERAT-CAC has better crosstalk suppression capability under the edge effect compared with FNS-FPF-CAC, FNS-FTF-CAC and 3D-DPS-CAC, along with smaller area overhead and lower transmission power.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsVol. 45(4)
Peking University Shenzhen Hospital (CN)
Affordable and clean energy
Openalex Percentile: Top 50%
Geochemistry and Geologic Mapping
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A Joint Data Transmission Scheme With Improved CAC for 3D-SICs Based on Multiple TSV Subarrays · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2025) | TGRS Research Map | TGRS