MAD-Flow: An Efficient Deployment Flow for Memory-Bank-Based Anomaly Detection on FPGA-SoCs

Industrial anomaly detection requires real-time, low-power edge computing solutions, yet state-of-the-art memory-bank-based algorithms face significant deployment barriers due to memory footprint constraints and computational latency bottlenecks in k-nearest neighbor (KNN) search operations. This paper presents MAD-Flow, a comprehensive hardware-software co-design framework specifically engineered to enable efficient deployment of memory-bank-based anomaly detection algorithms on field programmable gate array system-on-chip (FPGA-SoC) platforms. MAD-Flow addresses these fundamental challenges through systematic integration of established FPGA technologies: leveraging deep learning processing units (DPUs) for quantized ResNet-50 feature extraction, together with custom accelerators generated through high-level synthesis (HLS) for KNN search and on-chip block RAM (BRAM) caching. The framework incorporates mixed-precision optimization with INT8 DNN backbone and INT4 KNN operations, complemented by system-level pipelining to maximize hardware utilization. Implemented on a Xilinx ZCU104 platform, MAD-Flow achieves 68.21 frames per second (FPS) throughput while maintaining competitive detection accuracy with 97.5% image-level and 97.7% pixel-level area under the receiver operating characteristic (AUROC) curve on the MVTec AD dataset. The system demonstrates exceptional energy efficiency at 13.37 FPS/W and computational efficiency at 78.9 giga operations per second per watt (GOPS/W), representing 24.7× and 83.5× improvements over graphics processing unit (GPU) and ARM-based platform, respectively. These results establish MAD-Flow as a practical solution for power-constrained industrial environments, demonstrating the feasibility of efficient edge-based anomaly detection systems.