Automated Anomaly Detection in C4 Wafer Mapping via Multi-Resolution Graph Neural Networks

**Abstract:** This paper introduces a novel approach to automated anomaly detection in capacitance-voltage (C-V) wafer mapping data utilizing multi-resolution graph neural networks (MR-GNNs). Traditional methods for identifying defects in wafer mapping often struggle with subtle anomalies and require substantial manual intervention. Our MR-GNN architecture leverages hierarchical graph representations to capture both local and global spatial dependencies, enabling the accurate identification of complex defect patterns with significantly improved precision and recall compared to established statistical and machine learning techniques. The system is immediately deployable for semiconductor manufacturing process control, offering a potential 15-20% reduction in scrapped wafers and a material cost savings exceeding $5 million annually.