DESIGN A CIRCUIT LEVEL LOW LEAKAGE AND ROBUST FLIP LECTOR APPROACH FOR SRAM CELL

In static random access memory (SRAM) cells, leakage power, stability, and speed have become significant challenges with the scale-down of technology. This paper presents a proposed Flip LECTOR approach. In the LECTOR approach, a leakage-controlled transistor (LCT) is always near its "cut-off" voltage for any input supply. In the GALEOR approach, gated transistors NMOS and PMOS are unsuitable for passing the VDD and ground at pullup (PUN) and pulldown (PDN), respectively. In MTCMOS, gated transistors may fail the gates, which reduces the noise margin. Also, due to additional mask layers, the fabrication process becomes complex. Hence, due to the above approaches, the operation of the 6T SRAM cell was vitiated. There is also signal quality contention, but this method does not have these problems because the adjacent LCT is always close to its linear voltage when one of the transistors in the SRAM cell is either PMOS or NMOS and "ON." LCT increases the resistance, which reduces leakage power. When compared to a 6T SRAM, LECTOR, GALEOR, and MTCMOS at 1V, the proposed method reduces the leakage power 2.55×, 5.84×, 1.08×, and 1.52× during read operation respectively. It is also 1.57×, 24×, and 1.15× improved during the write operation. The read delay is 3.82× and 3.83× smaller than that of LECTOR and GALEOR. The write delay is 1.21×, 1.26×, and 1.37× less than that of LECTOR, GALEOR, and MTCMOS. Proposed approach WSNM is 1.92×, 1.03×, 1.78×, and 1.43× better than 6T SRAM, LECTOR, GALEOR, and MTCMOS.